The present invention relates to a semiconductor structure and a method of fabricating the same. More particularly, the present invention relates to an interconnect structure in which an alloy liner is positioned between an underlying diffusion barrier and a seed layer. The alloy liner of the present invention is comprised of a reaction product between the underlying diffusion barrier and the seed layer. The invention also provides methods of forming such an interconnect structure.
Generally, semiconductor devices include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, -based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than silicon dioxide.
In current technologies, a material stack including, from bottom to top, a TaN diffusion barrier, a Ta layer for adhesion and electromigration redundancy/enhancement, and a Cu alloy plating seed layer is used for advanced interconnect applications. Although Cu alloy plating seed layers such as, for example, CuIr, CuAl and CuRu, are known to improve seed layer coverage, e.g., provide conformality enhancement, the use of Cu alloy plating seed layers increases the resistance of the final interconnect structure. Also, higher resistivity of Cu alloy seed layer could result in more challenges, e.g., uniformity control during a later Cu plating process.
In view of the above, there is a need for providing an interconnect structure in which a Cu alloy plating seed layer can be employed without increasing the resistance within the final interconnect structure and no drawbacks for subsequent Cu plating.